1. Field of the Invention
This invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly to a dynamic RAM having a 3-dimensional memory cell structure and a method for manufacturing the same.
2. Description of the Related Art
A dynamic RAM is one of the semiconductor memory devices in which the most advanced fine patterning process is applied. Various types of new memory cell structures have been proposed to develop dynamic RAMs with higher integration density. A trench transistor cross-point type memory cell (which is hereinafter referred to as a TTC type memory cell) is known as a memory cell structure of the dynamic RAM having the highest integration density at present. For example, the TTC type memory cell is disclosed in Technical Digest International Electron Devices Meeting 1985, pp. 714 to 717, "A TRENCH TRANSISTOR CROSS-POINT DRAM CELL" W. F. Richardson et al.
The equivalent circuit of the TTC type memory cell is the same as the equivalent circuit of a so-called one-transistor/one-capacitor type memory cell and has a feature that a capacitor is arranged at every intersection between the bit line and word line.
The TTC type memory cell has an advantage that the memory cell can be integrated with a high integration density but at the same time it has the following defects.
First, in the TTC type memory cell, a MOS transistor acting as a transfer gate is formed by use of the side wall of a trench which is formed by etching the semiconductor substrate. For this reason, various interface states occur in the interface between the gate insulation film and the semiconductor substrate, making the characteristic of the MOS transistor unstable and lowering the driving ability thereof.
Secondly, since bit lines formed of n-type impurity diffused layers are arranged in opposition to one another in the main surface area of the semiconductor substrate, it becomes necessary to form an element isolation region for isolating the memory cells from each other between the bit lines.
Thirdly, since the n-type impurity diffused layer acting as the bit line is formed to surround the trench portion, the area thereof becomes large. For this reason, a parasitic capacitance between the bit line and the substrate becomes large, causing the operation speed to be lowered.